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Soft-Switching in DC-DC Converters:

Principles, Practical Topologies,

Design Techniques, Latest Developments

Raja Ayyanar

Arizona State University

Ned Mohan

University of Minnesota

Eric Persson

International Rectifier

Some of the slides in this presentation are used for the course EE5741 Advanced Power Electronics given by Prof Robbins and Prof Mohan at the University of Minnesota

© 2002, N. Mohan, R. Ayyanar, E. Persson

APEC 2002

1

 

Objectives

•What is soft-switching?

•Basic principles

•Concentration on a few popular topologies

•Design techniques

•Computer simulations

•New developments

2

What is Soft-Switching

•Switching transitions occur under favorable conditions – device voltage or current is zero

•Reduced switching losses, switch stress, possibly low EMI, easier thermal management

•A must for very high frequency operation, (also medium frequency at high power levels)

•Usually involves compromises in conduction loss, switch rating, passive components etc.

4

Relationship Between Efficiency

and Power Density

 

500

 

 

 

 

 

 

 

400

 

 

 

 

Pout

 

 

 

 

 

η =

 

300

 

 

 

Pout

+Ploss

Rating

 

 

 

 

 

 

η

200

Ploss = 20W

 

∴Pout =

1-η Ploss

Power

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

Ploss

=10W

 

 

 

 

 

 

 

 

 

 

 

0.8

0.84

0.88

0.92

0.96

 

 

 

 

 

Efficiency

 

 

 

 

5

Hard-Switching

iL

iT +

 

v

 

-

T

 

Vd

+

 

 

vdiode

iL ≈ Io

vgate

 

vT

idiode

 

iT

v

 

diode

Ploss

 

P

∝ f

t

+t

 

 

sw

 

s c(on)

c(off )

6

 

 

 

 

 

MOSFET Characteristics

Output characteristics

Cross-sectional view of an n-channel MOSFET

source

 

 

gate

 

 

n+

Cgs

p

 

p

n+

 

 

 

 

Cds

 

 

Cgd

 

Transfercharacteristics

 

n

-

drain-body

 

 

 

 

depletion layer

 

 

 

n+

 

 

 

 

 

drain

 

 

7

MOSFET Characteristics

 

Df

Io

Vin

Cgd

iD = f (Vgs )

 

RG

VGG Cgs

MOSFET model valid in

 

Variation of capacitances with Vds

active and cutoff regions

 

 

 

 

8

Simulation of Hard Switching Converters

 

L2

 

 

40nH

I3

 

D2

 

1A

 

80

 

 

R3

 

 

1m

 

V1

R2 M1

Ideal diode

50V

IRF150 25.0

IRF150

0

20

vDS

10

vGS

iD

0

gate input

-10

0s

0.5us

1.0us

1.5us

2.0us

2.5us

3.0us

3.5us

4.0us

9

V(M1:d)/4

ID(M1)*2

V(R2:2)

V(V3:+)

 

 

 

 

 

Time

Simulation of Hard Switching Converters

• Diode reverse recovery

55

 

 

 

vds

PARAMETERS:

 

R_LOAD = 1

40

 

 

fs = 100k

 

 

V1

20

100

MUR2020R

vgs

 

 

 

MUR2020R

5A I1

D5

 

 

Io

 

 

 

ids

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-10

30.4us

30.8us

31.2us

31.6us

32.0us

 

32.4us

32.8us

2us

 

33.6us

34.0us

30.0us

 

 

-I(R3)

V(M1:1)/2

I(I1)

 

Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38.5

 

 

 

 

 

 

38.5

 

 

 

 

 

 

 

 

 

 

vds

 

 

 

 

 

 

 

 

 

 

v

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ds

 

20.0

 

 

 

ids

vgs

 

20.0

vgs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Io

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ids

 

 

 

 

 

 

Io

0

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30.9154us

30.9500us

31.0000us

31.0500us

31.1000us

31.1299us

32.95us

33.00us

33.05us

33.10us

33.15us

33.20us

33.25us

33.30us33.34us

-I(R3)

V(M1:1)/3

V(M1:2)

I(I1)

 

 

 

Time

 

 

 

-I(R3)

V(M1:1)/3

V(M1:2) I(I1)

 

 

 

 

 

 

 

 

 

 

 

 

 

Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R2

 

M1

 

 

MTB20N20E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V1 = 0

 

V4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V2 = 15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TD = 1u

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TR = 1n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF = 1n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PW = 2u

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PER = {1/fs}

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MTB20N20E

10

Problems of Hard-Switching

•Switching losses

•Device stress, thermal management

•EMI due to high di/dt and dv/dt

•Energy loss in stray L and C

Possible Solutions (combination)

•Snubbers to reduce di/dt and dv/dt

Þusually no change in losses (unless loss recovery)

•Circuit layout to reduce stray inductances

•Gate drive

Þcircuit layout

Þturn on / off speeds

•Soft switching to achieve ZVS and/or ZCS

11

Snubbers

•Passive components (R, L, C) and a diode to shape switching trajectories

Turn-on snubber (seldom used)

 

 

 

iT

 

 

 

+ v

 

 

 

-

T

 

 

 

 

V

L

s

 

Rs

d

 

 

 

Io

Þ At turn-on

iT (t)=Vd t Ls

•low di/dt

•lower turn-on losses in the device

•low reverse recovery current

vT

t

0

iT

t

0

ÞPrice to be paid at turn-off

•1/2 LI2 energy dissipated during off interval

•off interval > 2 to 3 times LS/RS time constant

•switch voltage rating increases by RSIO

12

Turn-off Snubbers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

iT

 

 

 

 

 

 

 

iCS

At turn-off

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

D

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vd

 

 

 

 

 

 

 

 

 

 

 

 

-T

 

 

 

 

 

 

 

 

 

S

•

while vT builds up

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

iT

= Io -iC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Io

 

(iC

flows through DS )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

•

switch turn-off loss decreases

iT

 

 

 

 

 

•

lower dv/dt

 

 

 

CS =0

 

Issues at turn-on

 

Io

 

 

 

 

 

 

 

CS1

 

• 1/2 CV2 energy dissipated in RS and switch

 

CS3

CS2

 

•

switch current rating increases by V

/ R S

0

 

 

 

•

d

 

0

 

 

 

V

ON interval > 2 to 3 times RSCS time constant

 

 

 

 

vT

 

 

 

CS

3

> CS

> CSd

 

 

 

 

 

 

2

1

 

 

 

13

Soft-Switching

•ZVS (Zero Voltage Switching)

•ZCS (Zero Current Switching) Advantages

-Lower losses (may be !)

-Low EMI (may be !)

-Allows high frequency operation

14

ZVS (Zero Voltage Switching)

Turn ON

Turn OFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Switch voltage brought to zero

• Low-loss transition

before gate voltage is applied

• Parallel capacitor as a

• Ideal, zero-loss transition

loss-less snubber

•Preferred scheme for very high frequency applications using MOSFETs

15

ZCS (Zero Current Switching)

Turn OFF

• Switch current brought to zero before gate voltage is removed

• Ideal, zero-loss transition

Turn ON

• Low-loss transition

• Series inductor as a loss-less snubber

• Energy in junction capacitance is lost

Best suited for converters with IGBTs due to tail current at turn-off

16

ZVS and Hard-Switched Waveforms

 

Zero-voltage switched

 

 

 

 

 

 

 

Hard-switched

 

12V

vdrain-source

vdrain-source

 

vgate-source

 

vgate-source

 

 

 

 

 

 

 

0V

 

 

0V

-12V

-12V

17

An Example: Zero Voltage Transition (ZVT)

 

Synchronous Buck Converter

 

 

 

 

vC+ (0)=0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

At t =0, T + is turned off

 

 

vC- (0)=Vd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

+

 

 

 

iC+

vC+ +vC- =Vd

 

T

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

iL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

 

 

D

+

 

iL

0

Vd

 

 

 

 

 

 

 

A

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

-

 

 

i

 

 

 

T

 

 

 

 

 

 

 

-

+ V

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

o

 

 

 

 

D-

C-

 

 

 

 

 

 

 

 

 

18

Zero Voltage Transition (ZVT)

Since

 

 

v

 

+

+v

-

=Vd

 

 

 

 

C

 

 

C

 

 

 

 

dv

 

+

 

 

 

 

dv

-

 

Cs

 

C

 

 

+Cs

 

 

C

 

=0

dt

 

 

 

dt

 

 

 

 

 

 

 

 

 

 

∴ i

 

+

+i

- =0

 

 

 

 

C

 

 

 

 

C

 

 

 

 

 

 

 

 

T

+

Cs+

i

+

 

 

 

 

C

 

 

 

 

 

 

 

 

Vd

+

 

 

D

+

 

 

 

 

A

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

 

T-

 

 

iC-

 

 

 

 

 

 

 

 

D-

Cs-

 

 

 

 

 

 

 

iL

L

+ Vo

Also, iC+ - iC- =iL

∴ iC+ =-iC- = i2L

Vd

∴ vC+ =0

vC- =Vd

0

 

•At the end of this charge/discharge interval, positive iL is carried by D-

•Subsequently, T- is turned on; iL must

reverse direction

19

Zero Voltage Transition

 

 

 

 

 

 

 

 

vA (t)

 

 

 

 

 

 

 

 

 

 

T

+

Cs+

iC

+

 

 

V

 

 

 

 

 

 

Vo

 

 

 

 

 

 

 

 

d

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

 

 

D+

 

 

iL

0

t0

t’

t"

t1

t’

t2

t3

t

Vd

 

A

 

 

 

 

-

T-

 

iC

 

L

 

 

0

0

 

1

 

 

 

 

 

 

-

+ V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

iL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

o

 

 

 

 

 

 

 

 

 

 

D-

Cs-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

t

Conducting

T+

 

 

 

D-

 

T-

 

 

D+

 

T+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Devices

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

None

 

 

 

 

None

 

 

 

 

 

 

None

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

Simulation of a ZVT Buck Converter

 

 

 

PARAMETERS:

 

 

 

 

PulseWidth = 4.5us

 

R7

M1

 

TDLY1 = 5.5us

 

 

TDLY2 = 0.5us

 

V7

 

 

 

IRF150

L1

Period = 10us

 

25

 

V1 TD = {TDLY1}

 

 

 

21V

 

20uH

 

 

 

 

IC = 2A

 

 

R8

M2

 

C2

R6

 

 

 

1000uF

10.0

V8

 

 

IC = 10V

IRF150

 

 

25

 

 

 

TD = {TDLY2}

 

 

ZVT_buck.opj

 

 

 

 

0

 

 

 

 

20

 

 

 

 

vDS

 

gate

 

 

 

input

 

 

10

vGS iL

0

iD

-10

-20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

9us

10us

11us

12us

13us

14us

15us

16us

17us

 

V(M2:d)/2

ID(M2)*2

V(M2:g)

I(L1)*2

 

V(V8:+)

Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Classification of

Soft-Switching Schemes

•Load Resonant Converters

•Converters with Resonant Switches (Quasi- resonant, Multi-resonant)

•Resonant Transition Converters

– ZVT and ZCT

22

Phase Shift Controlled

Full-Bridge Converter (ZVT)

Makes use of switch capacitances and transformer leakage inductance and magnetizing current

 

T+

T+

 

 

 

 

A

B

 

 

 

+

A

 

Da+

D+

Io

 

a

b

Vd -

 

b

T-

T- B

Da-

 

 

Db-

 

 

A

B

 

 

 

•Poles A & B switched at nearly 50% duty-cycle

•Output voltage regulation is achieved by phase modulating the two pole outputs

47

Switching waveforms

vA

+

T+

DA+

DB+

vB

 

T+

 

 

A

 

B

 

Vin

A

iAB

+vAB

vAB

-

 

 

DA

T-

B

 

 

T-

 

 

 

A

B

 

 

-

 

 

DB-

iAB

 

 

 

 

t

In pole A

 

 

+Vd

T

 

- to T

 

⇒ vAB =0

 

+

 

A

A

 

 

 

T

+ to T

-

⇒ vAB =0

-Vd

A

 

A

 

 

 

 

 

 

 

 

In pole B

TB- to TB+ ⇒ vAB =+Vd 0

T

+ to T

0

- ⇒ vAB =-Vd

B

B

 

 

 

48

Transitions - Pole B

 

 

T

-

to T

+

 

TB- to TB+

 

 

B

 

 

 

B

 

 

vAB

 

 

+

 

 

 

 

 

 

iAB

 

T+

TB

 

i

L

Da+

 

 

+

A

 

 

 

 

 

Io

 

A

 

 

 

 

 

a

 

Vd -

B

 

 

 

 

 

b

t

 

 

T-

 

 

 

 

 

Db-

 

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TB+ to TB-

•vAB =+Vd 0

•iL stays at Io

0

•vAB =-Vd

•iL stays at - Io

49

Transitions - Pole A

T+

 

TB+

+

 

A

 

iL

Da

+

 

 

a

 

 

 

Vd -

A

 

B

b

-

 

Db-

 

 

TA

 

 

 

T

+ to T

-

⇒ vAB =0

-Vd

A

A

 

 

vAB

T

+ to T

-

Io

A

A

 

iAB

 

 

 

 

 

t

•All four diodes conduct

•Leakage inductance resonates with switch capacitance

•Determination of Tdel critical for ZVS design

•Load dependent ZVS

50

Methods to increase ZVS range

• Use of external series inductor

+

 

iAB

Lo

 

 

 

+

+

Vin

A Lseries

B

vrect

Vo

-

 

 

-

 

 

 

 

 

 

vAB

Disadvantages

 

Loss of volt-sec

 

iAB

0

higher turns-ratio

 

 

 

 

higher

increased

 

 

conduction loss

vrect

 

VA ratings

 

 

 

Load dependent ZVS

 

 

left-leg

51

Use of magnetizing current

+

 

imag

 

 

 

 

Vin

 

iload +imag

 

A

B

Disadvantages

 

-

 

higher conduction loss due to

 

 

• peak circulating current

vAB

 

• current through right-leg

imag

MOSFETs

 

• peak magnetizing current

 

 

 

 

independent of Vin

 

2

 

 

left-leg

52

 

 

Factors Affecting ZVS

ZVS Load Range

Capacitance across MOSFETs

–internal and external

Leakage inductance

Delay time

Magnetizing current

Design of other parameters like Lo, Co, transformer etc identical to hard switched PWM

53

 

 

 

 

 

 

Designing for ZVS

 

 

MOSFET voltage during critical

 

 

 

 

turn-on transition

 

 

 

 

vds

 

 

 

 

 

 

 

 

 

 

 

Leq sin(ωt )

 

 

v

=V

-

(

I

 

 

+I

refl )

 

 

 

ds

in

 

 

mag _ pk

 

2Cds

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

t

ω = 2p L C

ds

 

 

 

 

 

p

LLk 2Cds

 

 

eq

 

 

 

Conditions for ZVS

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. (Imag _ pk +Irefl )

Leq

=Vin,max

 

 

 

 

 

 

 

 

 

 

 

 

2Cds

 

 

 

2. T

=

p L

.2C

ds

delay

 

2

eq

 

 

 

 

 

 

54

Designing for ZVS

A Possible Design Approach Using MathCAD

• Sweep for all practical values of

Cds - based on limiting voltage rise during turn-off Tdelay - as a percentage of switching period

•Calculate required Imag,pk and Llk for each set

•Calculate switch peak current and RMS current

Turn-off loss Conduction loss

• Calculate total losses. Iterate for different ZVS ranges

55

Designing for ZVS

Total Losses

(W)

j

i

j ⇒ Cds

i ⇒ Tdel

56